32bit TX System RISC TX19A Family TMP19A43CD/CZXBG
Rev2.0
2007.Aug.31
TMP19A43
32-bit RISC Microprocessor - TX19 Family
TMP19A43CZXBG, CDXBG TMP19A43FZXBG, FDXBG 1. Overview and Features
The TX19 family is a high-performance 32-bit RISC processor series that TOSHIBA originally developed by integrating the MIPS16TMASE (Application Specific Extension), which is an extended instruction set of high code efficiency. TMP19A43 is a 32-bit RISC microprocessor with a TX19A processor core and various peripheral functions integrated into one package. It can operate at low voltage with low power consumption. Features of TMP19A43 are as follows:
RESTRICTIONS ON PRODUCT USE
070122EBP
* The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.
021023_A
* The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.
070122_C
* The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
TMP19A43 (rev2.0) 1-1
Overview and Features
TMP19A43
(1) TX19A processor core 1) Improved code efficiency and operating performance have been realized through the use of two ISA (Instruction Set Architecture) modes - 16- and 32-bit ISA modes. * * 2) The 16-bit ISA mode instructions are compatible with the MIPS16TMASE instructions of superior code efficiency at the object level. The 32-bit ISA mode instructions are compatible with the TX39 instructions of superior operating performance at the object level.
Both high performance and low power dissipation have been achieved. High performance * * * * * * * Almost all instructions can be executed with one clock. High performance is possible via a three-operand operation instruction. 5-stage pipeline Built-in high-speed memory DSP function: A 32-bit multiplication and accumulation operation can be executed with one clock. Optimized design using a low power dissipation library Standby function that stops the operation of the processor core Independency of the entry address Automatic generation of factor-specific vector addresses Automatic update of interrupt mask levels
Product name TMP19A43CZXBG TMP19A43CDXBG TMP19A43FZXBG TMP19A43FDXBG Built-in ROM 384Kbyte 512Kbyte 384Kbyte (Flash) 512Kbyte (Flash) Built-in RAM 20Kbyte 24Kbyte 20Kbyte 24Kbyte
Low power dissipation
3)
High-speed interrupt response suitable for real-time control * * *
(2) Internal program memory and data memory
* * *
ROM correction function: 1 word x 8 blocks, 8 words x 4 blocks Expandable to 16 megabytes (for both programs and data) External data bus: Separate bus/multiplexed bus Chip select/wait controller Activated by an interrupt or software Data to be transferred to internal memory, internal I/O, external memory, and external I/O : 16 channels 16-bit interval timer mode 16-bit event counter mode 16-bit PPG output (every 4 channels, synchronous outputs are possible) Input capture function 2-phase pulse input counter function (4 channels assigned to perform this function): Multiplicationby-4 mode : Coexistence of 8- and 16-bit widths is possible. : 4 channels : 8 channels (2 interrupt factors)
(3) External memory expansion
(4) DMA controller * * * * * * *
(5) 16-bit timer
TMP19A43 (rev2.0) 1-2
Overview and Features
TMP19A43
(6) 32-bit timer * * * 32-bit input capture register 32-bit compare register 32-bit time base timer : 4 channels : 8 channels : 1 channel : 1 channel : 3 channels : 3 channels
(7) Clock timer (8) General-purpose serial interface * * (9) High-speed serial interface
Selectable between the UART mode and the synchronization mode Selectable between the UART mode and the high-speed synchronization mode (maximum speed: 10 Mbps in the high-speed synchronization mode @40MHz) : 1 channel
2
(10) Serial bus interface * * * * * * * (11) 10-bit A/D converter (with S/H) Fixed channel/scan mode Single/repeat mode Top-priority conversion mode Timer monitor function Conversion time 1.15 sec(@ 40MHz)
Selectable between the I C bus mode and the clock synchronization mode : 16 channels Start by an external trigger, and the internal timer activated by a trigger
(12) 8-bit D/A converter (13) Watchdog timer (14) Interrupt function * * *
: 2 channels : 1 channel
CPU: 2 factors ...................software interrupt instruction Internal: 46 factors.............The order of precedence can be set over 7 levels (except the watchdog timer interrupt). External: 48 factors ..........The order of precedence can be set over 7 levels. Because 32 factors are associated with KWUP, the number of interrupt factors is one.
(15) Input and output ports ...............143 terminals (16) Standby function * * * * Three standby modes (IDLE, SLEEP, STOP) Built-in PLL (multiplication by 4) Clock gear function: The high-speed clock can be divided into 3/4, 1/2, 1/4 or 1/8. Sub-clock: SLOW and SLEEP modes (32.768 kHz) (17) Clock generator
(18) Endian: Bi-endian (big-endian/little-endian) (19) Maximum operating frequency * * * * 40 MHz (PLL multiplication) Core: I/O and ADC: DAC: 1.35 V to 1.65 V 2.7 V to 3.6 V 2.3 V to 2.7 V (20) Operating voltage range
(21) Package P-FBGA193 (12 mm x 12 mm, 0.65 mm pitch)
TMP19A43 (rev2.0) 1-3
Overview and Features
TMP19A43
TX19 Processor Core TX19A CPU MAC 512K/384byte Flash/MASK ROM correction Clock generator (CG) External bus interface Clock timer (1ch) EJTAG 24K/20Kbyte RAM
DMAC (8ch) INTC
HSIO/UART 0 to 2 (3ch) I/O bus interface
16-bit TMRB 0 to 15 (16ch) 32-bit TMRC TBT (1ch) 32-bit TMRC Input Capture 0 to 3 (4ch) 32-bit TMRC Compare 0 to 7 (8ch) 10-bit ADC (16ch) 8-bit DAC (2ch)
PORT0 to PORT6 (also function as external bus I/F) PORT7 to PORT8 (also function to receive ADC inputs) PORT9 to PORTH (also function as functional pins) SIO/UART 0 to 2 (3ch) I2C/SIO (1ch)
WDT KWUP (32ch)
Fig. 1-1 TMP19A43 Block Diagram
TMP19A43 (rev2.0) 1-4
Overview and Features
TMP19A43
2.
2.1
Pin Layout and Pin Functions
This section shows the pin layout of TMP19A43 and describes the names and functions of input and output pins.
Pin Layout (Top view)
Fig. 2-1 Pin Layout Diagram (P-FBGA193) shows the pin layout of TMP19A43.
A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1
A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2
A3 B3
A4 B4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4
A5 B5 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5 T5 U5
A6 B6 D6 E6 F6
A7 B7 D7 E7
A8 B8 D8 E8
A9 B9
A10 A11 A12 A13 A14 A15 A16 A17 B10 B11 B12 B13 B14 B15 B16 B17 C16 C17 D16 D17 E16 E17 F16 F17 G16 H16 J16 K16 L16 M16 G17 H17 J17 K17 L17 M17 N17 P17 R17 T17 U17
D9 D10 D11 D12 D13 D14 E9 E10 E11 E12 E13 E14 F13 F14 G13 H13 J13 K13 L13 M13 G14 H14 J14 K14 L14 M14
N6 P6 T6 U6
N7 P7 T7 U7
N8 P8 T8 U8
N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14
T3 U3
T4 U4
N16 P16 R16 T9 T10 T11 T12 T13 T14 T15 T16 U9 U10 U11 U12 U13 U14 U15 U16
Fig. 2-1 Pin Layout Diagram (P-FBGA193)
TMP19A43 (rev2.0) 2-1
Pin Layout and Pin Functions
TMP19A43
2.2
Pin Numbers and Names
Table 2-1 shows the pin numbers and names of TMP19A43.
Table 2-1 Pin numbers and names
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C16 C17 D1 Pin Name DVSS P81/AN9/KEY05 P83/AN11/KEY07 P85/AN13/INT7 P87/AN15/INT9 DA0 CVREF0 DA1 CVREF1 PD2/HSCLK2/HCTS2 PE2/KEY10 PE5/KEY13 PE7/KEY15 X1 X2 CVCCH CVSS PF0/KEY16/DREQ0 P80/AN8/KEY04 P82/AN10/KEY06 P84/AN12/INT6 P86/AN14/INT8 P75/AN5/KEY01 P77/AN7/KEY03 PD6/KEY31/AFTRG PD4/TBCOUT PD1/HRXD2 PE1/KEY09 PE4/KEY12 PE6/KEY14 PA5/INT5/TB8IN1 PA6/ TB2IN0 PA7/TB2IN1 CVCCL PF2/KEY18/DREQ4 PF1/KEY17/DACK0 PA4/INT4/TB8IN0 XT2 PF4/KEY20/TCOUT4 Pin No. D2 D4 D5 D6 D7 D8 D9 D10 Pin Name PF3/KEY19/DACK4 P71/AN1 P73/AN3 P74/AN4/KEY00 P76/AN6/KEY02 PD5/TBDOUT PD3/TBBOUT PD0/HTXD2 Pin No. G2 G4 G5 G13 G14 G16 G17 H1 Pin Name P95/SCLK2/CTS2 P94/RXD2 P93/TXD2 PH1/TPC1/TPD1 PH7/TPC7/TPD7 PCST4 DCLK PC1/TCOUT0 PC0/TBTIN/KEY30 P97/TBAOUT DVCC3 PH2/TPC2/TPD2 TRST TMS EJE PC4/TCOUT3 PC3/TCOUT2 PC2/TCOUT1 DVCC15 PH3/TPC3/TPD3 DINT TDO DVSS PC7/SCK PC6/SI/SCL PC5/SO/SDA DVSS DVCC15 TOVR/TSTA TDI TCK PB2/HTXD0 PB1/TB3IN1 PB0/TB3IN0 TEST1 DVSS PG0/TPD0 PG1/TPD1 PG2/TPD2 Pin No. Pin Name Pin No. Pin Name P33/WAIT/RDY P45/BUSMD P46/ENDIAN P37/ALE/TC3IN
P34/BUSRQ/TBEOUT
M1 PB5/HTXD1 R2 M2 PB4/HSCLK0/HCTS0 R16 M4 PB3/HRXD0 R17 M5 TEST4 T1 M13 FVCC3 T2 M14 PG3/TPD3 T3 M16 PG4/TPD4 T4 M17 PG5/TPD2 T5
P30/RD P02/D2/AD2 P06/D6/AD6
D11 PE0/KEY8 H2 D12 PE3/KEY11 H4 D13 PA2/INT2/TB7IN0 H5 D14 PH4/TPC4/TPD4 H13 D16 PA3/INT3/TB7IN1 H14 D17 XT1 H16 E1 PF6/KEY22/TCOUT6 H17 E2 PF5/KEY21/TCOUT5 J1 E4 P70/AN0 J2 E5 P72/AN2 J4 E6 VREFH J5 E7 AVSS J13 E8 DAVCC J14 E9 DAVREF J16 E10 DAGND J17 E11 DVCC3 K1 E12 PA0/INT0/TB6IN0 K2 E13 PA1/INT1/TB6IN1 K4 E14 PH5/TPC5/TPD5 K5 E16 PCST0 K13 E17 PCST1 K14 F1 PF7/KEY23/TCOUT7 K16 F2 P92/TB8OUT K17 F4 P91/TB7OUT L1 F5 P90/TB6OUT L2 F6 AVCC3 L4 F13 PH0/TPC0/TPD0 L5 F14 PH6/TPC6/TPD6 L13 F16 PCST2 L14 F17 PCST3 L16 G1 P96/TB9OUT L17
N1 PB7/HSCLK1/HCTS1 T6 P12/D10/AD10/A10 N2 PB6/HRXD1 T7 P16/D14/AD14/A14 N4 P00/D0/AD0 T8 P21/A17/A1/TB0IN1 N5 P04/D4/AD4 T9 P24/A20/A4/TB4IN0 N6 P10/D8/AD8/A8 T10 P26/A22/A6/TB5IN0 N7 P14/D12/AD12/A12 T11 P52/A2/INTE N8 FVCC3 T12 P56/A6/TB2OUT/KEY28 N9 DVSS T13 P62/A10/SCLK0/CTS0 N10 DVCC15 T14 P66/A14/TB4OUT N11 P50/A0/INTC T15 P40/CS0/KEY24 N12 P54/A4/TB0OUT T16 P42/CS2/KEY26 N13 P60/A8/TXD0 T17 P44/SCOUT N14 P64/A12/RXD1/INTB U1 TEST2 N16 PG6/TPD6 U2 P35/BUSAK/TC1IN N17 PG7/TPD7 U3 P31/WR P1 BOOT U4 P03/D3/AD3 P2 P32/HWR/TC0IN U5 P07/D7/AD7 P4 P01/D1/AD1 U6 P13/D11/AD11/A11 P5 P05/D5/AD5 U7 P17/D15/AD15/A15 P6 P11/D9/AD9/A9 U8 P22/A18/A2/TB1IN0 P7 P15/D13/AD13/A13 U9 P25/A21/A5/TB4IN1 P8 P20/A16/A0/TB0IN0 U10 P27/A23/A7/TB5IN1 P9 P23/A19/A3/TB1IN1 U11 P53/A3/INTF P10 TEST0 U12 P57/A7/TB3OUT/KEY29 P11 P51/A1/INTD U13 P63/A11/TXD1 P12 P55/A5/TB1OUT U14 P67/A15/TB5OUT P13 P61/A9/RXD0/INTA U15 P41/CS1/KEY25 P14 P65/A13/SCLK1/CTS1 U16 P43/CS3/KEY27 P16 P47/TBFOUT U17 TEST3 P17 RESET R1 P36/RW/TC2IN
TMP19A43 (rev2.0) 2-2
Pin Layout and Pin Functions
TMP19A43
2.3
Pin Names and Functions
Table 2-2 through Table 2-7 show the names and functions of input and output pins. Table 2-2 Pin Names and Functions (1 of 6)
Pin name
P00-P07 D0-D7 AD0-D7 P10-P17 D8-D15 AD8-AD15 A8-A15 P20-P27 A16-A23 A0-A7
TB0IN0,TB0IN1 TB1IN0,TB1IN1 TB4IN0,TB4IN1 TB5IN0,TB5IN1
Number of pins 8
Input or output
Input/output Input/output Input/output Input/output Input/output Input/output Output Input/output Output Output Input Input Input Input Output
Output
Function
Port 0: Input/output port (with pull-up) that allows input/output to be set in units of bits Data (lower): Data bus 0 to 7 (separate bus mode) Address data (lower): Address data bus 0 to 7 (multiplexed bus mode) Port 1: Input/output port (with pull-up) that allows input/output to be set in units of bits Data (upper): Data bus 8 to 15 (separate bus mode) Address data (upper): Address data bus 8 to 15 (multiplexed bus mode) Address: Address bus 8 to 15 (multiplexed bus mode) Port 2: Input/output port (with pull-up) that allows input/output to be set in units of bits Address: Address bus 15 to 23 (separate bus mode) Address: Address bus 0 to 7 (multiplexed bus mode) 16-bit timer 0 input 0,1: For inputting the count/capture trigger of a 16-bit timer 0 16-bit timer 1 input 0,1: For inputting the count/capture trigger of a 16-bit timer 1 16-bit timer 4 input 0,1: For inputting the count/capture trigger of a 16-bit timer 4 16-bit timer 5 input 0,1: For inputting the count/capture trigger of a 16-bit timer 5 Port 30: Port used exclusively for output
Read: Strobe signal for reading external memory Port 31: Port used exclusively for output
Write: Strobe signal for writing data of D0 to D7 pins Port 32: Input/output port (with pull-up) Write upper-pin data: Strobe signal for writing data of D8 to D15 pins For inputting the capture trigger for 32-bit timer Port 33: Input/output port (with pull-up)
Wait: Pin for requesting CPU to put a bus in a wait state Ready: Pin for notifying CPU that a bus is ready Port 34: Input/output port (with pull-up) Bus request: Signal requesting CPU to allow an external master to take the bus control authority 16-bit timer E output: Pin for outputting 16-bit timer E Port 35: Input/output port (with pull-up) Bus acknowledge: Signal notifying that CPU has released the bus control authority in response to BUSRQ For inputting the capture trigger for 32-bit timer Port 36: Input/output port (with pull-up) Read/write: "1" shows a read cycle or a dummy cycle. "0" shows a write cycle. For inputting the capture trigger for 32-bit timer Port 37: Input/output port (with pull-up) Address latch enable (address latch is enabled only if access to external memory is taking place) For inputting the capture trigger for 32-bit timer Port 40: Input/output port (with pull-up)
8
8
P30
1
RD P31
WR P32 HWR TC0IN P33
WAIT RDY P34
BUSRQ
TBEOUT P35
1
Output
Output
1
Input/output Output Input Input/output
Input Input Input/output Input Output Input/output Output Input Input/output Output Input Input/output Output Input Input/output
1
1
1
BUSAK
TC1IN P36
R/W TC2IN P37
1
1
ALE TC3IN P40
1
CS0
KEY24 P41 1
Output Input Input/output Output Input 1 Input/output
Chip select 0: "0" is output if the address is in a designated address area. KEY on wake up input 24: (Dynamic pull up is selectable) Input with Schmitt trigger with Noise filter Port 41: Input/output port (with pull-up) Chip select 1: "0" is output if the address is in a designated address area. KEY on wake up input 25: (Dynamic pull up is selectable) Input with Schmitt trigger with Noise filter Port 42: Input/output port (with pull-up)
CS1
KEY25 P42
CS2
KEY26
Output Input
Chip select 2: "0" is output if the address is in a designated address area. KEY on wake up input 26: (Dynamic pull up is selectable) Input with Schmitt trigger with Noise filter
TMP19A43 (rev2.0) 2-3
Pin Layout and Pin Functions
TMP19A43
Table 2-3 Pin Names and Functions (2 of 6)
Pin name
P43 Number of pins 1
Input or output
Input/output Port 43: Input/output port (with pull-up)
Function
CS3
KEY27 P44 SCOUT P45 BUSMD 1
Output Input Input/output Output Input/output Input
Chip select 3: "0" is output if the address is in a designated address area. KEY on wake up input 27: (Dynamic pull up is selectable) Input with Schmitt trigger with Noise filter Port 44: Input/output port (with pull-up) System clock output: Selectable between high- and low-speed clock outputs, as in the case of CPU Port 45: Input/output port (with pull-up) Pin for setting an external bus mode: This pin functions as a multiplexed bus by sampling the "H (DVCC3) level" at the rise of a reset signal. It also functions as a separate bus by sampling "L" at the rise of a reset signal. When performing a reset operation, pull it up or down according to a bus mode to be used. Input with Schmitt trigger. (After a reset operation is performed, it can be used as a port.) Port 46: Input/output port (with pull-up) This pin is used to set a mode. It performs a big-endian operation by sampling the "H (DVCC3) level" at the rise of a reset signal, and performs a little-endian operation by sampling "L" at the rise of a reset signal. When performing a reset operation, pull it up or down according to the type of endian to be used. (After a reset operation is performed, it can be used as a port.) Input with Schmitt trigger Port 47: Input/output port (with pull-up) 16-bit timer F output: Pin for outputting a 16-bit timer F Port 5: Input/output port (with pull-up) that allows input/output to be set in units of bits Address: Address buses 0 to 3 (separate bus mode) Interrupt request pins C to F: Selectable between "H" level, "L" level, rising edge, and falling edge Input pin with Schmitt trigger with Noise filter Port 5: Input/output port (with pull-up) that allows input/output to be set in units of bits Address: Address buses 4 and 5 (separate bus mode) 16-bit timer 0 output: Pin for outputting a 16-bit timer 0 16-bit timer 1 output: Pin for outputting a 16-bit timer 1 Port 5: Input/output port (with pull-up) that allows input/output to be set in units of bits Address: Address buses 6 and 7 (separate bus mode) 16-bit timer 2 output: Pin for outputting a 16-bit timer 2 16-bit timer 3 output: Pin for outputting a 16-bit timer 3 KEY on wake up input 28 and 29: (Dynamic pull up is selectable) Input pin with Schmitt trigger with Noise filter Port 60: Input/output port (with pull-up) Address: Address bus 8 (separate bus mode) Sending serial data 0: Open drain output pin depending on the program used Port 61: Input/output port (with pull-up) Address: Address bus 9 (separate bus mode) Receiving serial data 0 Interrupt request pin A: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. Input pin with Schmitt trigger with Noise filter Port 62: Input/output port (with pull-up) Address: Address bus 10 (separate bus mode) Serial clock input/output 0 Handshake input pin Open drain output pin depending on the program used Port 63: Input/output port (with pull-up) Address: Address bus 11 (separate bus mode) Sending serial data 1: Open drain output pin depending on the program used Port 64: Input/output port (with pull-up) Address: Address bus 12 (separate bus mode) Receiving serial data 1 Interrupt request pin B: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. Input pin with Schmitt trigger with Noise filter
1
P46 ENDIAN
1
Input/output Input
P47 TBFOUT P50-P53 A0-A3 INTC-INTF
1 4
Input/output Output Input/output Output Input
P54,P55 A4,A5 TB0OUT TB1OUT P56,P57 A6,A7 TB2OUT TB3OUT KEY28,KEY29 P60 A8 TXD0 P61 A9 RXD0 INTA
2
2
Input/output Output Output Output Input/output Output Output Output Input Input/output Output Output Input/output Output Input Input
1
1
P62 A10 SCLK0 CTS0 P63 A11 TXD1 P64 A12 RXD1 INTB
1
Input/output Output Input/output Input Input/output Output Output Input/output Output Input Input
1
1
TMP19A43 (rev2.0) 2-4
Pin Layout and Pin Functions
TMP19A43
Table 2-4 Pin Names and Functions (3 of 6)
Pin name
P65 A13 SCLK1 CTS1 P66,P67 A14,A15 TB4OUT TB5OUT P70-P73 AIN0-AIN3 P74-P77 AIN4-AIN7
KEY00-KEY03
Number of pins 1
Input or output
Input/output Output Input/output Input Input/output Output Output Output Input Input Input Input Input Input Input Input Input Input
Function
Port 65: Input/output port (with pull-up) Address: Address bus 13 (separate bus mode) Serial clock input/output 1 Handshake input pin. Open drain output pin depending on the program used Port 6: Input/output port (with pull-up) that allows input/output to be set in units of bits Address: Address buses 14 and 15 (separate bus mode) 16-bit timer 4 output: Pin for outputting a 16-bit timer 4 16-bit timer 5 output: Pin for outputting a 16-bit timer 5 Port 7: Port used exclusively for input (with pull-up) Analog input: Input from A/D converter Port 7: Port used exclusively for input (with pull-up) Analog input: Input from A/D converter KEY on wake up input 00 to 03: (Dynamic pull up is selectable) Input pin with Schmitt trigger with Noise filter Port 8: Port used exclusively for input (with pull-up) Analog input: Input from A/D converter KEY on wake up input 04 to 07: (Dynamic pull up is selectable) Input pin with Schmitt trigger with Noise filter Port 8: Port used exclusively for input (with pull-up) Analog input: Input from A/D converter Interrupt request pins 6 to 9: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. Input pin with Schmitt trigger with Noise filter Port 9: Input/output port (with pull-up) that allows input/output to be set in units of bits 16-bit timer 6 output: Pin for outputting a 16-bit timer 6 16-bit timer 7 output: Pin for outputting a 16-bit timer 7 16-bit timer 8 output: Pin for outputting a 16-bit timer 8 Port 93: Input/output port (with pull-up) Sending serial data 2: Open drain output pin depending on the program used Port 94: Input/output port (with pull-up) Receiving serial data 2 Port 95: Input/output port (with pull-up) Serial clock input/output 2 Handshake input pin Open drain output pin depending on the program used Ports 96 and 97: Input/output port (with pull-up) that allows input/output to be set in units of bits 16-bit timer 9 output: Pin for outputting a 16-bit timer 9 16-bit timer A output: Pin for outputting a 16-bit timer A Port A0: Input/output port (with pull-up) 16-bit timer 6 input 0: For inputting the capture trigger of a 16-bit timer 6 Interrupt request pin 0: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. Input pin with Schmitt trigger with Noise filter Port A1: Input/output port (with pull-up) 16-bit timer 6 input 1: For inputting the capture trigger of a 16-bit timer 6 Interrupt request pin 1: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges Input pin with Schmitt trigger with Noise filter Port A2: Input/output port (with pull-up) 16-bit timer 7 input 0: For inputting the capture trigger of a 16-bit timer 7 Interrupt request pin 0: Selectable "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. Input pin with Schmitt trigger with Noise filter Port A3: Input/output port (with pull-up) 16-bit timer 7 input 1: For inputting the capture trigger of a 16-bit timer 7 Interrupt request pin 1: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges. Input pin with Schmitt trigger with Noise filter
2
4 4
P80-P83 AIN8-AIN11
KEY04-KEY07
4
P84-P87 AIN12-AIN15 INT6-9
4
P90-P92 TB6OUT TB7OUT TB8OUT P93 TXD2 P94 RXD2 P95 SCLK2 CTS2 P96,P97 TB9OUT TBAOUT PA0 TB6IN0 INT0
3
1 1 1
Input/output Output Output Output Input/output Output Input/output Input Input/output Input/output Input Input/output Output Output Input/output Input Input
2
1
PA1 TB6IN1 INT1
1
Input/output Input Input
PA2 TB7IN0 INT2
1
Input/output Input Input
PA3 TB7IN1 INT3
1
Input/output Input Input
TMP19A43 (rev2.0) 2-5
Pin Layout and Pin Functions
TMP19A43
Table 2-5 Pin Names and Functions (4 of 6)
Pin name
PA4 TB8IN0 INT4 Number of pins 1
Input or output
Input/output Input Input
Function
Port A4: Input/output port (with pull-up) 16-bit timer 8 input 0: For inputting the capture trigger of a 16-bit timer 8 Interrupt request pin 0: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges Input pin with Schmitt trigger with Noise filter Port A5: Input/output port (with pull-up) 16-bit timer 8 input 1: For inputting the capture trigger of a 16-bit timer 8 Interrupt request pin 1: Selectable between "H" level, "L" level, rising edge, falling edge, and both rising and falling edges Input pin with Schmitt trigger with Noise filter Port A6: Input/output port (with pull-up) 16-bit timer 2 input 0: For inputting the capture trigger of a 16-bit timer 2 Port A7: Input/output port (with pull-up) 16-bit timer 2 input 1: For inputting the capture trigger of a 16-bit timer 2 Port B0: Input/output port (with pull-up) 16-bit timer 3 input 0: For inputting the capture trigger of a 16-bit timer 3 Port B1: Input/output port (with pull-up) 16-bit timer 3 input 1: For inputting the capture trigger of a 16-bit timer 3 Port B2: Input/output port (with pull-up) Sending serial data 0 at high speeds: Open drain output pin depending on the program used Port B3: Input/output port (with pull-up) Receiving serial data 0 at high speeds Port B4: Input/output port (with pull-up) High-speed serial clock input/output 0 Handshake input pin: Open drain output pin depending on the program used Port B5: Input/output port (with pull-up) Sending serial data 1 at high speeds: Open drain output pin depending on the program used Port B6: Input/output port (with pull-up) Receiving serial data 1 at high speeds Port B7: Input/output port (with pull-up) High-speed serial clock input/output 1 Handshake input pin: Open drain output pin depending on the program used Port C0: Input/output port (with pull-up) 32-bit time base timer input: For inputting a 32-bit time base timer KEY on wake up input 30: (Dynamic pull up is selectable) Input with Schmitt trigger with Noise filter Ports C1 to C4: Input/output ports (with pull-up) that allow input/output to be set in units of bits Outputting 32-bit timer if the result of a comparison is a match Port C5: Input/output port (with pull-up) Pin for sending data if the serial bus interface operates in the SIO mode Pin for sending and receiving data if the serial bus interface operates in the I2C mode Open drain output pin depending on the program used Input with Schmitt trigger Port C6: Input/output port (with pull-up) Pin for receiving data if the serial bus interface operates in the SIO mode Pin for inputting and outputting a clock if the serial bus interface operates in the I2C mode Open drain output pin depending on the program used Input with Schmitt trigger Port C7: Input/output port (with pull-up) Pin for inputting and outputting a clock if the serial bus interface operates in the SIO mode Open drain output pin depending on the program used
PA5 TB8IN1 INT5
1
Input/output Input Input
PA6 TB2IN0 PA7 TB2IN1 PB0 TB3IN0 PB1 TB3IN1 PB2 HTXD0 PB3 HRXD0 PB4 HSCLK0 HCTS0 PB5 HTXD1 PB6 HRXD1 PB7 HSCLK1 HCTS1 PC0 TBTIN KEY30 PC1-PC4 TCOUT0TCOUT3 PC5 SO SDA
1
1 1 1 1 1
Input/output Input Input/output Input Input/output Input Input/output Input Input/output Output Input/output Input Input/output Input/output Input Input/output Output Input/output Input Input/output Input/output Input Input/output Input
1 1 1
1
4
Input/output Output
1
Input/output Output Input/output
PC6 SI SCL
1
Input/output Input Input/output
PC7 SCK
1
Input/output Input/output
TMP19A43 (rev2.0) 2-6
Pin Layout and Pin Functions
TMP19A43
Table 2-6 Pin Names and Functions (5 of 6)
Pin name
PD0 HTXD2 PD1 HRXD2 PD2 HSCLK2 HCTS2 PD3-PD5 TBBOUTTBDOUT PD6 ADTRG KEY31 PE0-PE7
KEY08-KEY15
Number of pins 1 1 1
Input or output
Input/output Output Input/output Input Input/output Input/output Input Input/output Output
Function
Port D0: Input/output port (with pull-up) Sending serial data 2 at high speeds: Open drain output pin depending on the program used Port D1: Input/output port (with pull-up) Receiving serial data 2 at high speeds Port D2: Input/output port (with pull-up) High-speed serial clock input/output 2 Handshake input pin: Open drain output pin depending on the program used Ports D3 to D5: Input/output ports (with pull-up) that allow input/output to be set in units of bits 16-bit timers B, C and D outputs: Pin for outputting 16-bit timers B, C and D Port D6: Input/output port (with pull-up) that allows input/output to be set in units of bits Pin (with Schmitt trigger) for starting A/D trigger or A/D converter from an external source KEY on wake up input 31: (Dynamic pull up is selectable) Input with Schmitt trigger with Noise filter Port E: Input/output port (with pull-up) that allows input/output to be set in units of bits KEY on wake up input 08 to 15: (Dynamic pull up is selectable) Input with Schmitt trigger with Noise filter Port F: Input/output port (with pull-up) that allows input/output to be set in units of bits DMA request signals 0 and 4: For inputting the request to transfer data by DMA from an external I/O device to DMAC0 or DMAC4 KEY on wake up input 16 to 19: (Dynamic pull up is selectable) Input with Schmitt trigger with Noise filter Port F: Input/output port (with pull-up) that allows input/output to be set in units of bits DMA acknowledge signals 0 and 4: Signal showing that DREQ0 and DREQ4 have acknowledged a DMA transfer request KEY on wake up input 16 to 19: (Dynamic pull up is selectable) Input with Schmitt trigger with Noise filter Port F: Input/output port (with pull-up) that allows input/output to be set in units of bits KEY on wake up input 20 to 23: (Dynamic pull up is selectable) Input with Schmitt trigger Outputting 32-bit timer if the result of a comparison is a match with Noise filter Port G: Input/output port (with pull-up) that allows input/output to be set in units of bits Outputting trace data from the data access address: Signal for DSU-ICE Port H: Input/output port (with pull-up) that allows input/output to be set in units of bits Outputting trace data from the program counter: Signal for DSU-ICE Outputting trace data from the data access address: Signal for DSU-ICE Debug clock: Signal for DSU-ICE DSU-ICE enable: Signal for DSU-ICE (with Schmitt trigger) (with pull-up) with Noise filter PC trace status: Signal for DSU-ICE Debug interrupt: Signal for DSU-ICE (input with Schmitt trigger and pull-up) with Noise filter Outputting the status of PD data overflow status: Signal for DSU-ICE Test clock input: Signal for testing DSU-ICE (with Schmitt trigger and pull-up) with Noise filter Test mode select input: Signal for testing DSU-ICE (with Schmitt trigger and pull-up) Test data input E: Signal for testing JTAG (with Schmitt trigger and pull-up) Test data output: Signal for testing DSU-ICE Test reset input: Signal for testing DSU-ICE (with Schmitt trigger and pull-down) with Noise filter Reset: Initializing LSI (with pull-up) Input with Schmitt trigger with Noise filter Pin for connecting a high-speed oscillator (X1: Input with Schmitt trigger) Pin for connecting a low-speed oscillator (XT1: Input with Schmitt trigger)
3
1
Input/output Input Input Input/output Input Input/output Input Input
8
PF0,PF2 DREQ0,4
KEY16,KEY18
2
PF1,PF3 DACK0,4
KEY17,KEY19
2
Input/output Output Input
PF4-PF7
KEY20-KEY23 TCOUT4TCOUT7
4
Input/output Input Output Input/output Output Input/output Output Output Output Input Output Input Output Input Input Input Output Input Input Input/output Input/output
PG0-PG7 TPD0-TPD7 PH0-PH7 TPC0-TPC7 TPD0-TPD7 DCLK EJE PCST4-0 DINT TOVR/TSR TCK TMS TDI TDO TRST
8 8
1 1 4 1 1 1 1 1 1 1 1 2 2
RESET
X1/X2 XT1/XT2
TMP19A43 (rev2.0) 2-7
Pin Layout and Pin Functions
TMP19A43
Table 2-7 Pin Names and Functions (6 of 6)
Pin name
BOOT Number of pins 1
Input or output
Input
Function
Pin for setting a single boot mode: This pin goes into single boot mode by sampling "L" at the rise of a reset signal. It is used to overwrite internal flash memory. By sampling "H (DVCC3) level" at the rise of a reset signal, it performs a normal operation. This pin should be pulled up under normal operating conditions. Pull it up when resetting. (With pull-up) Pin (H) for supplying the A/D converter with a reference power supply Connect this pin to AVCC3 if the A/D converter is not used. Pin for supplying the A/D converter with a power supply. Connect it to a power supply even if the A/D converter is not used. A/D converter GND pin (0 V). Connect this pin to GND even if the A/D converter is not used. Pin (L) for supplying the A/D converter with a reference power supply TEST pin: To be fixed to DVCC3 (with Schmitt trigger) TEST pin: To be fixed to DVCC3 TEST pin: Set to OPEN. TEST pin: Set to OPEN. TEST pin: Set to OPEN. Pin for supplying a high-frequency oscillator with power: 1.5 V power supply Pin for supplying a low-frequency oscillator with power: 3 V power supply Oscillator GND pin (0 V) Power supply pin: 1.5 V power supply Power supply pin: 3 V power supply Power supply pin: GND pin (0 V) Power supply pin for the D/A converter: 2.5 V power supply If the D/A converter is not used, connect (fix) this pin to GND. Reference power supply pin for the D/A converter If the D/A converter is not used, connect (fix) this pin to GND. GND pin (0 V) for the D/A converter Connect this pin to GND even if the D/A converter is not used. Pin for connecting a stabilizing capacitor to the D/A converter Pin for connecting a stabilizing capacitor to the D/A converter D/A converter 0 output pin D/A converter 1 output pin
VREFH AVCC3 AVSS TEST0 TEST1 TEST2 TEST3 TEST4 CVCCH CVCCL CVSS DVCC15 DVCC3 DVSS DAVCC CVREF DAGND CVREF0 CVREF1 DA0 DA1
1 1 1 1 1 1 1 1 1 1 1 3 4 5 1 1 1 1 1 1 1
Input - - Input Input Input Input Input - - - - - - - - - - - Output Output
TMP19A43 (rev2.0) 2-8
Pin Layout and Pin Functions
TMP19A43
2.4
Pin Names and Power Supply Pins
Table 2-8 Pin Names and Power Supplies Pin name P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH Power supply DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 AVCC3 AVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 Pin name PCST4-0 DCLK EJE TRST TDI TDO TMS TCK DINT TOVR/TSTA BUSMD BOOT X1, X2 XT1, XT2 RESET DA0,1 Power supply DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 DVCC3 CVCCH CVCCL DVCC3 DAVCC
2.5
Pin Numbers and Power Supply Pins
Table 2-9 Pin Numbers and Power Supplies
Power supply DVCC15 DVCC3 AVCC3 FVCC3 CVCCH CVCCL DAVCC
Pin number J5, K13, N10 E11, H5 F6 M13, N8 A16 B17 E8
Voltage range 1.35 V to 1.65 V 1.65 V to 3.6 V 2.7 V to 3.6 V 2.7 V to 3.6 V 1.35 V to 1.65 V 2.7 V to 3.6 V 2.3 V to 2.7 V
TMP19A43 (rev2.0) 2-9
TMP19A43
3.
Processor Core
The TMP19A43 has a high-performance 32-bit processor core (TX19A processor core). For information on the operations of this processor core, please refer to the "TX19A Family Architecture." This chapter describes the functions unique to the TMP19A43 that are not explained in that document.
3.1
Reset Operation
To reset the device, ensure that the power supply voltage is in the operating voltage range, the oscillation of the internal high-frequency oscillator has stabilized at the specified frequency and that the RESET input has been "0" for at least 12 system clocks (2.4 s during external 10 MHz operation). Note that the PLL multiplication clock is quadrupled and the clock gear is initialized to the 1/8 mode during the reset period. When the reset request is authorized, the system control coprocessor (CP0) register of the TX19A processor core is initialized. For further details, please refer to the chapter about architecture. After the reset exception handling is executed, the program branches off to the exception handler. The address to which the program branches off to (address where exception handling starts) is called an exception vector address. This exception vector address of a reset exception (for example, nonmaskable interrupt) is 0xBFC0_0000H (virtual address). The register of the internal I/O is initialized. The port pin (including the pin that can also be used by the internal I/O) is set to a general-purpose input or output port mode.
(Note 1) Set the RESET pin to "0" before turning the power on. Perform the reset after the power supply voltage has stabilized sufficiently within the operating range. (Note 2) After turning the power on, make sure that the power supply voltage and oscillation have stabilized, wait for 500 s or longer, and perform the reset. (Note 3) In the FLASH program, the reset period of 0.5 uS or longer is required independently of the system clock. (Note 4) The reset operation can alter the internal RAM state, but does not alter data in the backup RAM.
TMP19A43 (rev2.0) 3-1
Processor Core
TMP19A43
4.
Memory Map
Fig. 4-1 shows the memory map of the TMP19A43FDXBG/TMP19A43CDXBG.
Virtual address 0xFFFF FFFF 0xFF00 0000 Kseg2 (1 GB) 0XBFC7 0xBFC0 0000 0xA000 0000 0x8000 0000 16 MB reserved Internal ROM area 0x4007 FFFF projection 0x4000 0000 Inaccessible Internal ROM 0x0007 FFFF 0x0000 0000 512 MB 0x1FC7 FFFF 0x1FC0 0000 Kseg1 (cash disabled) Kuseg (2 GB) Kseg0 (cash enabled)
Reserved for debugging (2 MB)
Physical address 16 MB reserved Kseg2 (cash enabled) 16 MB reserved Internal I/O 0xFFFF E000 Built-in RAM area 0xFFFF DFFF (24 KB) 0xFFFF 8000 Inaccessible
16 MB reserved
0xFF3F FFFF 0xFF20 0000 0xFF00 0000 0x1FC7 FFFF
Inaccessible
Kuseg (cash enabled)
User program area Maskable interrupt area Exception vector area 0x1FC0 0400
0x1FC0 0000
Fig. 4-1 Memory Map Fig. 4-2 shows the memory map of the TMP19A43FZXBG/TMP19A43CZXBG.
Virtual address 0xFFFF FFFF 0xFF00 0000 Kseg2 (1 GB) 0XBFC5 FFFF 0xBFC0 0000 0xA000 0000 0x8000 0000 16 MB reserved Internal ROM area 0x4005 FFFF projection 0x4000 0000 Inaccessible Internal ROM 0x0005 FFFF 0x0000 0000 384 MB 0x1FC5 FFFF 0x1FC0 0000 Kseg1 (cash disabled) Kuseg (2 GB) Kseg0 (cash enabled)
Reserved for debugging (2 MB)
Physical address 16 MB reserved Kseg2 (cash enabled) 16 MB reserved Internal I/O 0xFFFF E000 Built-in RAM area 0xFFFF DFFF (20 KB) 0xFFFF 9000 Inaccessible
16 MB reserved
0xFF3F FFFF 0xFF20 0000 0xFF00 0000 0x1FC5 FFFF
Inaccessible
Kuseg (cash enabled)
User program area Maskable interrupt area Exception vector area 0x1FC0 0400
0x1FC0 0000
Fig. 4-2 Memory Map
TMP19A43 (rev2.0) 4-1
Memory Map
TMP19A43
(Note 1) The internal ROM is mapped to: 0x1FC0_0000-0x1FC5_FFFF (384 KB) 0x1FC0_0000-0x1FC7_FFFF (512 KB) The internal RAM is mapped to: 0xFFFF_9000-0xFFFF_DFFF (20 KB) 0xFFFF_8000-0xFFFF_DFFF (24 KB) (Note 2) For the TMP19A43, a physical space of only 16 MB is available as external address space to be accessed. It is possible to place this 16-MB physical address space in a chip select area of your choice inside the 3.5-GB physical address space of the CPU. Access to internal memory, internal I/O space and reserved areas is given priority over access to the external address space. Therefore, access to the external address space is denied if any of the internal memory, internal I/O space or reserved areas are being accessed. (Note 3) Do not place an instruction in the last four words of a physical area, specifically the last four words of an area where memory is mounted for external ROM extension (this varies depending on the system of the user). Internal ROM: 0x1FC5_FFF0-0x1FC5_FFFF (384 KB) Internal ROM: 0x1FC7_FFF0-0x1FC7_FFFF (512 KB)
TMP19A43 (rev2.0) 4-2
Memory Map
TMP19A43
5.
Clock/Standby Control
The system operation modes contain the standby modes in which the processor core operations are stopped to reduce power dissipation. Fig. 5-1 State Transition Diagram of Each Operation Mode is shown below.
Reset Reset has been performed IDLE mode (CPU stop) (I/O selective operation) Instruction Interrupt NORMAL mode (fc/gear value) Instruction Interrupt STOP mode (Entire circuit stop)
(a) State Transition Diagram of Single Clock Mode
Reset
Reset has been performed
IDLE mode (CPU stop) (I/O selective operation)
Instruction Interrupt
Interrupt
NORMAL mode (fc/gear value)
Instruction
Instruction
Interrupt
Instruction
SLEEP mode (fs only)
Instruction Interrupt
SLOW mode (fs)
Interrupt
Instruction
STOP mode (Entire circuit stop)
(b) State Transition Diagram of Dual Clock Mode
Fig. 5-1 State Transition Diagram of Each Operation Mode
Reset
Reset has been performed
NORMAL mode fc = fpll = foscx4 fsys = fc/8 fsys = fosc/2 fperiph =fgear= fsys
Fig. 5-2 Default State of the System Clock
TMP19A43 (rev2.0) 5-1
Clock/Standby Control
TMP19A43
fosc: fpll: fc: fs: fgear: fsys:
Clock frequency to be input via the X1 and X2 pins Clock frequency multiplied (quadrupled) by the PLL High-frequency clock frequency Low-frequency clock frequency Clock frequency selected by the system control register SYSCR1 in the clock generator System clock frequency The CPU, ROM, RAM, DMAC, INTC and HSIO all operate according to this clock. The internal peripheral I/O operates according to the fsys/2 clock.
fperiph: Clock frequency selected by SYSCR1 (Clock to be input to the peripheral I/O prescaler)
5.1
Clock System Block Diagram
5.1.1
Main System Clock
* * * Allows for oscillator connection or external clock input. Clock gear (3/4, 1/2, 1/4, 1/8) (Default is 1/8.) Input frequency (high frequency)
Input frequency range 8 to 10 (MHz)* Maximum operating frequency 40 MHz Lowest operating frequency 4 MHz
* Clock gear 1/8 (default) is used when 8 MHz (MIN) is input. * Input frequency (low frequency)
Input frequency range 30 KHz to 34 KHz Maximum operating frequency 34 kHz Lowest operating frequency 15 kHz
When the low-speed clock gear 1/2 is used: 15 KHz (MIN)
(Note)
(precautions for switching the high-speed clock gear) Switching of clock gear is executed when a value is written to the SYSCR1 register. There are cases where switching does not occur immediately after the change in the register setting but the original clock gear is used for execution of instructions. If it is necessary to use the new clock for execution of the instructions following to the clock gear switching instruction, insert a dummy instruction (to execute a write cycle). To use the clock gear, ensure that you make the time setting such that Tn of the prescaler output from each block in the peripheral I/O is calibrated to TnTMP19A43 (rev2.0) 5-2
Clock/Standby Control
TMP19A43
5.1.2
Clock Gear
* * The high-speed clock is divided into 3/4, 1/2, 1/4 or 1/8. The internal I/O prescaler clock T0: fperiph/2, fperiph/4, fperiph/8 and fperiph/16
SYSCR0 SYSCR2
SYSCR1 ADC conversion clock fperiph (to peripheral I/O) fsgear
Warm-up timer fc fs fsgear 1/2
fgear
fsys SYSCR0 X1 X2 SYSCR1 3/4 1/2 1/4 1/8 PLL SYSCR1 SYSCR1 Eight frequency divisions after the reset has been performed fpll = fosc x 4 CPU
High-speed oscillator
fosc
fsys SYSCR0
ROM RAM
DMAC INTC fperiph /2 /4 /8 /16 HSIO SYSCR0 XT1 XT2 KWUP /2 Peripheral I/O ADC,TMRB/C, SIO, SBI, WDT, Port 2-phase pulse input counter Clock timer
Low-speed oscillator
Clock timer
fs to Warm-up timer T0 Input to peripheral I/O prescaler TMRB/C, SIO, SBI,
fsgear
2-phase pulse input counter SYSCR3 fsys/2
SCOUT
Fig. 5-3 Clock and Standby Related Block Diagram
TMP19A43 (rev2.0) 5-3
Clock/Standby Control
TMP19A43
5.2
5.2.1
CG Registers
System Control Registers
Bit symbol Read/Write After reset Function 7 XEN R/W 1 High-speed oscillator 6 XTEN R/W 0 Low-speed oscillator 5 RXEN R/W High-speed oscillator after the STOP mode is released 4 RXTEN R/W Low-speed oscillator after the STOP mode is released 3 R This can be read as "0." 2 WUEF R/W Control of warm-up timer (WUP) for oscillator 0 write: don't care 1 write: WUP Start 1 0 PRCK1 PRCK0 R/W R/W Select prescaler clock 00: fperiph/16 01: fperiph/8 10: fperiph/4 11: fperiph/2
SYSCR0
LITTLE BIG
(0xFFFF_EE00) (0xFFFF_EE03)
0: Stop 1: Oscillation
0: Stop 1: Oscillation 0: Stop 1: Oscillation 0: Stop 1: Oscillation
7 SYSCR1
6
SYSCKFLG
LITTLE BIG
(0xFFFF_EE01) (0xFFFF_EE02)
Bit symbol Read/Write After reset Function
R This can be read as "0."
SYSCR2
LITTLE BIG
(0xFFFF_EE02) (0xFFFF_EE01)
Bit symbol Read/Write After reset Function 7 DRVOSCH R/W 0 High-speed oscillator current control 0: High capability 1: Low capability 7 Bit symbol Read/Write After reset Function R This can be read as "0."
R 0 System clock status flag 0: High speed (fc) 1: Low speed (fs) 6 R/W 0 This can be read as "0."
5 SYSCK R/W 0 Select system clock
4 FPSEL R/W 0 Select fperiph
3 SGEAR R/W Select gear of low-speed clock
0 read: WUP finished 1 read: WUP operating 2 1 0 GEAR2 GEAR1 GEAR0 R/W R/W R/W 1 1 1 Select gear of high-speed clock (fc) 000: fc 001: reserved 010: fc3/4 011: reserved 100: fc/2 101: reserved 110: fc/4 111: fc/8
0: High speed (fgear) 0: fgear 1: Low 1: fc speed (fs) 5 4 WUPT1 WUPT0 R/W R/W 1 0 Select oscillator warm-up time 00: No WUP 01: 2 /Input frequency 10: 214 /Input frequency 11: 216 /Input frequency
0: fs/1 1: fs/2 3 2 STBY1 STBY0 R/W R/W 1 1 Select standby mode 00: Reserved 01: STOP 10: SLEEP 11: IDLE
1 R This can be read as "0."
0 DRVE R/W 0 1: Drive the pin even in the STOP mode.
SYSCR3
LITTLE BIG
(0xFFFF_EE03) (0xFFFF_EE00)
6 5 SCOSEL1 SCOSEL0 R/W R/W 0 1 Select SCOUT output 00: fsgear 01: fsys/2 10: fsys 11: T0
4 ALESEL R/W 1 Set ALE output width 0: fsysx1 1: fsysx2
3
2 R 0
1
0
This can be read as "0."
* *
Don't switch the SYSCK and the GEAR<2:0> simultaneously. If the system enters the STOP mode with SYSCR2 set at 1 (low capability), the setting will change to 0 (high capability) after the STOP mode is released.
* *
SYSCK can be switched when both of XEN and XTEN are set to "1." Be sure to set the RXEN and the RXTEN to 1 (oscillation) for the oscillator selected at the SYSCK. If a wrong setting is made, the oscillator selected by the SYSCK will oscillate.
*
The clock that has been selected with SYSCK oscillates without fail after making clear the STOP mode.
TMP19A43 (rev2.0) 5-4
Clock/Standby Control
TMP19A43
5.3
System Clock Controller
By resetting the system clock controller, the controller status is initialized to ="1,"="0" and ="111," and the system clock fsys changes to fc/8. (fc=fosc (original oscillation frequency)x4, because the original oscillation is quadrupled by PLL.) For example, when a 10-MHz oscillator is connected to the X1 or X2 pin, fsys becomes 5 MHz (=10x4x1/8) after the reset. Similarly, when the oscillator is not connected and an external oscillator is used to input a clock instead, fsys becomes the frequency obtained from the calculation "input frequencyx4x1/8."
5.3.1
Oscillation Stabilization Time (Switching between the NORMAL and SLOW modes)
The warm-up timer is provided to confirm the oscillation stability of the oscillator when it is connected to the oscillator connection pin. The warm-up time can be selected by setting the SYSCR2 depending on the characteristics of the oscillator. The SYSCR0 is used to confirm the start and completion of warm-up through software (instruction). After the completion of warm-up is confirmed, switch the system clock (SYSCR1). When clock switching occurs, the current system clock can be checked by monitoring the SYSCR1. Table 5-1 shows the warm-up time when switching occurs.
(Note 1) The time for warm-up is required even when an external clock (oscillator, etc.) is used
and providing stable oscillation because the internal PLL is used even in this case.
(Note 2) The warm-up timer operates according to the oscillation clock, and it can contain errors if there is any fluctuation in the oscillation frequency. Therefore, the warm-up time should be taken as approximate time.
Table 5-1 Warm-up Time
Warm-up time options SYSCR2 01 (28/oscillation frequency) 10 (214/oscillation frequency) 11 (216/ oscillation frequency) High-speed clock (fosc) 25.6 (s) 1.638 (ms) 6.554 (ms) Low-speed clock (fs) 7.8 (ms) 500 (ms) 2000 (ms) These values are calculated under the following conditions: fosc = 10 MHz, fs = 32.768 kHz
TMP19A43 (rev2.0) 5-5
Clock/Standby Control
TMP19A43
Transition from the NORMAL mode to the SLOW mode SYSCR2="xx": Select the warm-up time SYSCR0="1": Enable the low-speed oscillation (fs) SYSCR0="1": Start the warm-up timer (WUP) SYSCR0 Read: Wait until the state becomes "0" (WUP is finished) SYSCR1="1": Switch the system clock to low speed (fs) SYSCR1Read: Confirm that the current state is "1" (the current system clock is fs) SYSCR0="0": Disable the high-speed oscillation (fosc) Transition from the SLOW mode to the NORMAL mode SYSCR2="xx": Select the warm-up time SYSCR0="1": Enable the high-speed oscillation (fosc) SYSCR0="1": Start the warm-up timer (WUP) SYSCR0 Read: Wait until the state becomes "0" (WUP is finished) SYSCR1="0": Switch the system clock to high speed (fgear) SYSCR1Read: Confirm that the current state is "0" (the current system clock is fgear) SYSCR0="0": Disable the low-speed oscillation (fs) (Note) In the SLOW mode, the CPU operates with the low-speed clock, and the INTC, the clock timer, the 2-phase pulse input counter, the KWUP (dynamic pull-up), the IO port and the EBIF (external bus interface) are operable. Stop other internal peripheral functions before the system enters the SLOW mode.
5.3.2
System Clock Pin Output Function
The system clock, fsys, fsys/2 or fs, can be output from the P44/SCOUT pin. By setting the port 4 related registers, P4CR to "1" and P4FC to "1," the P44/SCOUT pin becomes the SCOUT output pin. The output clock is selected by setting the SYSCR3. Table 5-2 shows the pin states in each standby mode when the P44/SCOUT pin is set to the SCOUT output.
Table 5-2 SCOUT Output State in Each Standby Mode
Mode
SCOUT selection
NORMAL
SLOW
Standby mode IDLE SLEEP STOP
= "00" = "01" = "10" = "11"
Output the fsgear clock. Output the fsys/2 clock. Output the fsys clock. Output the T0 clock. Fixed to "0" or "1."
(Note)
The phase difference (AC timing) between the system clock output by the SCOUT and the internal clock is not guaranteed.
TMP19A43 (rev2.0) 5-6
Clock/Standby Control
TMP19A43
5.3.3
Reducing the Oscillator Driving Capability
This function is intended for restricting oscillation noise generated from the oscillator and reducing the power dissipation of the oscillator when it is connected to the oscillator connection pin. Setting the SYSCR2 to "1" reduces the driving capability of the high-speed oscillator. (low capability) This is reset to the default setting "0." When the power is turned on, oscillation starts with the normal driving capability (high capability). This is automatically set to the high driving capability state ( ="0") whenever the oscillator starts oscillation due to mode transition. Reducing the driving capability of the high-speed oscillator
fOSC C1 Oscillator C2 X2 pin X1 pin Enable oscillation SYSCR2
Fig. 5-4 Oscillator Driving Capability
5.3.4
Clock Frequency Division for Low-Speed System Clock
The low-speed clock (fs) can be divided into two by setting the system control register SYSCR1 to "1." This reduces the power dissipation in the SLOW mode. Set the clock frequency division during high-speed oscillation.
TMP19A43 (rev2.0) 5-7
Clock/Standby Control
TMP19A43
5.4
Prescaler Clock Controller
Each internal I/O (TMRB0-F, TMRC, SIO0-2 and SBI) has a prescaler for dividing a clock. The clock T0 to be input to each prescaler is obtained by selecting the "fperiph" clock at the SYSCR1 and the SYSCR0 and then dividing the clock according to the setting of SYSCR0. After the controller is reset, fperiph/16 is selected as T0. For details, please refer to Fig. 5-5 System Clock Transition Diagram.
5.5
Clock Multiplication Circuit (PLL)
This circuit outputs the fpll clock that is quadruple of the high-speed oscillator output clock, fosc. This lowers the oscillator input frequency while increasing the internal clock speed.
TMP19A43 (rev2.0) 5-8
Clock/Standby Control
TMP19A43
5.6
Standby Controller
The TX19A core has several low-dissipation modes. To shift to the STOP, SLEEP or IDLE (Halt or Doze) mode, set the RP bit in the CPO status register, and then execute the WAIT instruction. Before shifting to the mode, you need to select the standby mode at the system control register (SYSCR2). The IDLE, SLEEP and STOP modes have the following features: IDLE: Only the CPU is stopped in this mode. The internal I/O has one bit of the ON/OFF setting register for operation in the IDLE mode in the register of each module. This enables operation settings for the IDLE mode. When the internal I/O has been set not to operate in the IDLE mode, it stops operation and holds the state when the system enters the IDLE mode. Table 5-3 shows a list of IDLE setting registers.
Table 5-3 Internal I/O setting registers for the IDLE mode
Internal I/O TMRB0-F
TMRC
IDLE mode setting register TBxRUN
TCCR
SIO0-3 HSIO0-3 I2C/SIO(SBI) A/D converter WDT
SCxMOD1 HSCxMOD1 SBIBR1 ADMOD1 WDMOD
(Note 1) The Halt mode is activated by setting the RP bit in the status register to "0," executing the WAIT command and shifting to the standby mode. In this mode, the TX19A processor core stops the processer operation while holding the status of the pipeline. The TX19A gives no response to the bus control authority request from the internal DMA, so the bus control authority is maintained in this mode. (Note 2) The Doze mode is activated by setting the RP bit in the status register to "1" and shifting to the standby mode. In this mode, the TX19A processor core stops the processer operation while holding the status of the pipeline. The TX19A can respond to the bus control authority request given from the outside of the processor core.
SLEEP: Only the internal low-speed oscillator, the clock timer, the 2-phase pulse input counter and the dynamic pull-up circuit (KWUP) operate. STOP: All the internal circuits are brought to a stop. The standby mode selection ..Status |
